The makers of a new non-volatile RAM said the memory is ready to move from a prototype to a fabrication facility, where 1TB chips the size of a postage stamp will be produced and tested.
Silicon Valley start-up Crossbar expects some of its 3D Restive RAM (3D RRAM) products to be out in 2016 as memory in wearable devices, with high-density storage devices like solid-state drives arriving within 18 months after that.
RRAM starts out with an advantage over NAND flash, which has been approaching a density dead-end. RRAM is natively denser than NAND, with higher performance. Crossbar’s 3D RRAM also has high native endurance, with the ability to sustain 100,000 write cycles, according to Sylvain Dubois, Crossbar’s vice president of marketing and business development.
An artists rendition of Crossbar’s RRAM memory. Tiny conductive filaments crisscross and connect silicon layers to represent a bit of data. Credit: Crossbar
Crossbar solved a key tech issue that enabled it to move to the next phase of development
A microscopic sideview photo of a Resistive RAM circuit where tiny conductive filaments crisscross and connect silicon layers to represent a bit of data.
Because of its greater density, RRAM will be able to use silicon wafers that are half the size used by current NAND flash fabricators. In a single chip, it has nearly 10 times the capacity of NAND flash and uses 20 times less power to store a bit of data. It also sports 100 times lower latency than NAND flash, meaning performance is massively improved, according to Crossbar.
And because RRAM is fully compatible with the standard manufacturing processes already used in NAND fabrication, no changes will be needed in manufacturing facilities.
But before it could send its technology to the factory, Crossbar had to overcome a major technological hurdle — error-causing electron leaks between memory cells.
Electron leakage is a common problem in non-volatile memory, even in today’s NAND flash solid-state drives (SSDs). As the size of transistors shrink below 20 nanometers, and chip density is increased, bits stored in tiny cells leak through to adjacent cells, creating data errors.
A diagram depicting leakage also called “sneak path” current between adjacent cells in an RRAM chip.
Samsung, Intel, Micron and other SSD makers have increased error correction code on their devices to address the problem. And more than one company has turned to 3D NAND, which stacks cells up to 32-layers high to increase density, offering some capacity breathing room without requiring a further cell size reduction.
The most-dense process for creating silicon flash memory cells to store data on planar (2D) NAND is between 10 nanometer (nm) and 19nm in size. To give some idea of how small that is, a nanometer is one-billionth of a meter, and a human hair is 3,000 times thicker than NAND flash made with 25nm process technology. There are 25 million nanometers in an inch.
Crossbar’s 3D RRAM starts at 20nm process technology.
NAND flash uses transistors or a charge to trap (also known as Charge Trap Flash) and store a bit of data in a silicon cell. By comparison, RRAM uses tiny conductive filaments that crisscross and connect silicon layers to represent a bit of data.
In RRAM, the top metal layer creates a conductive electrode, the middle is an amorphous silicon switching medium, and the lower layer is nonmetallic. When the programming voltage is applied between the two electrodes, the nanoparticles of the top electrode diffuse in the switching material and create a filament; the memory cell is conductive when the filament contacts the bottom electrode. When the reverse voltage is applied between the two electrodes, the filament is pushed back and disappears. The memory cell is non-conductive.
RRAM will be able to use silicon wafers that are half the size used by current NAND flash fabricators. In a single chip, it has nearly 10 times the capacity of NAND flash and uses 20 times less power to store a bit of data.
Crossbar refers to the electron leakage between cells as “sneak path current,” which is inherent in RRAM memory.
To overcome the data error problem with its RRAM, Crossbar invented a way to hide adjacent cells from those being programmed to store data, thereby insulating them from unintentional changes. It did that by setting a specific voltage range for cells. Cells programmed between -1 volt and +1 volt are ignored, and anything outside that range can be programmed to hold new data.
The technology is called a Field-Assisted Superlinear Threshold (FAST) selector device, and it suppressed the sneak path current — marking another significant milestone needed to commercialize RRAM memory for high-density data applications.
“When we unveiled Crossbar RRAM eighteen months ago, we laid out aggressive plans to deliver a new generation of memory capable of scaling to 1 terabyte on a chip the size of a postage stamp,” said Crossbar CEO George Minassian. “With this latest achievement, we are one step closer to commercialization, enabling the implementation of RRAM technology in commercial products; a ground breaking achievement that will redefine what is possible with enterprise storage and high-capacity non-volatile [systems-on-a-chip] memories.”